實驗指導手冊：基于4001老百匯網站SF1開發板的FPGA入門

目錄

1 4001老百匯網站 SF1 開發板和工具概述 .............................................................................1

1.1 SF1 開發板...................................................................................................................... 1

1.1.1 FPGA 邏輯......................................................................................................................1

1.1.2 RISC-V 處理器...............................................................................................................2

1.2 開發工具 ........................................................................................................................ 3

1.2.1 TD 概述...........................................................................................................................3

2 使用 TD 完成 FPGA 邏輯設計 ...............................................................................5

2.1 TD 使用流程................................................................................................................... 5

2.1.1 新建工程文件 ................................................................................................................5

2.2.2 添加 RTL 文件...............................................................................................................6

2.2.3 邏輯綜合 ........................................................................................................................7

2.2.4 管腳約束 ........................................................................................................................8

2.2.5 生成 bit 文件..................................................................................................................9

2.2.6 使用 FD 進行 RISC-V 的編程和調試 ........................................................................10

2.2 使用 Modelsim 完成功能仿真 .................................................................................... 23

2.2.1 實驗概述 ......................................................................................................................23

2.2.2 實驗原理 ......................................................................................................................23

2.2.3 創建 TD 工程...............................................................................................................23

2.2.4 打開 modelsim 新建工程文件.....................................................................................24

2.2.5 加入源文件并編譯 ......................................................................................................25

2.2.6 仿真源文件 ..................................................................................................................27

2.2.7 代碼覆蓋率仿真（選做） ..........................................................................................29

2.3 協同 Modelsim 完成時序仿真 .................................................................................... 34

2.3.1 實驗原理 ......................................................................................................................34

2.3.1 物理仿真 ......................................................................................................................35

2.3.2 修改優化設置 ..............................................................................................................35

2.3.3 聯合 Modelsim 進行仿真............................................................................................39

3 FPGA 的基本 IP 核調用.........................................................................................43

3.1 鎖相環 .......................................................................................................................... 43

3.1.1 實驗原理 ......................................................................................................................43

3.1.2 新建工程 ......................................................................................................................43

I3.1.3 工程中例化創建的 PLL IP..........................................................................................47

3.2 調用 SRAM 實驗步驟 ................................................................................................. 49

3.2.1 Basic 配置 ....................................................................................................................49

3.2.2 Port A options 配置......................................................................................................49

3.2.3 Port B options 配置 ......................................................................................................50

3.2.4 Other options 配置 ........................................................................................................50

3.5 調用 FIFO 實驗步驟.................................................................................................... 50

4 基于 SF1 開發板完成 RISC-V 處理器的開發 ......................................................52

4.1 點亮流水燈................................................................................................................... 52

4.1.1 系統設計 ......................................................................................................................52

4.1.2 實驗步驟 ......................................................................................................................53

4.2 使用串口完成數據輸入和輸出................................................................................... 63

4.2.1 實驗概述 ......................................................................................................................63

4.2.2 系統設計 ......................................................................................................................63

4.2.3 工程建立 ......................................................................................................................64

4.2.4 編寫 C 代碼..................................................................................................................64

4.2.5 主頻設置 ......................................................................................................................67

4.2.6 串口波特率設置 ..........................................................................................................67

4.3.5 燒錄與結果查看 ..........................................................................................................68

4.3 實現 CORDIC 算法...................................................................................................... 69

4.3.1 實驗概述 ......................................................................................................................69

4.3.2 系統設計 ......................................................................................................................69

4.3.1 工程建立 ......................................................................................................................71

4.3.2 編寫 C 代碼..................................................................................................................71

4.3.3 燒錄與結果查看 ..........................................................................................................73

4.4 移植 FreeRTOS ............................................................................................................ 75

4.4.1 實驗概述 ......................................................................................................................75

4.4.2 系統設計 ......................................................................................................................76

4.4.3 TD 工程建立.................................................................................................................78

4.4.4 FD 工程建立.................................................................................................................84

4.4.5 編寫 C 代碼..................................................................................................................84

4.4.6 燒錄與結果查看 ..........................................................................................................89

II5 基于 SF1 開發板完成 FPGA 邏輯與 MCU 協同開發.........................................90

5.1 在 FPGA 邏輯部分設計 CORDIC 算法的 IP 核 ........................................................ 90

5.2 實驗原理 .........................................................................................................................90

5.2.1 系統設計 ......................................................................................................................90

5.2.2 工程建立 ......................................................................................................................93

5.2.3 CORDIC IP 核設計.......................................................................................................96

5.2.4 FD 工程建立...............................................................................................................102

6 4001老百匯網站 SF1 FPGA 開發板的圖像邊沿檢測系統設計...........................................108

6.1 概述：Canny 算法..................................................................................................... 108

6.2 邏輯設計 .................................................................................................................... 108

6.2.1 Canny 邊緣檢測算法的具體原理.............................................................................109

6.2.2 FPGA 端邏輯的設計與仿真.....................................................................................112

6.2.3 MCU 端代碼的設計 ..................................................................................................114

6.3 MCU 與 FPGA 協同完成系統設計........................................................................... 114

7 基于 SF1 的小游戲機設計...................................................................................120

7.1 實驗概述 .................................................................................................................... 120

7.2 實驗原理 .................................................................................................................... 120

7.2.1 系統設計 ....................................................................................................................120

7.2.2 FPGA 側硬件設計......................................................................................................121

7.2.3 MCU 側軟件設計 ....................................................................................................130

7.2.4 MCU 與 FPGA 通信..................................................................................................135

7.2.5 實驗步驟 ....................................................................................................................141

7.2.5 FD 工程建立...............................................................................................................150

7.2.6 關鍵模塊仿真波形 ....................................................................................................155

7.2.7 整體功能測試 ............................................................................................................157

以上僅目錄，不包含例程原理圖視頻等內容

如有需要請聯系大學計劃項目負責人：師妍

郵箱：yan.shi@anlogic.com

微信：tracykikicucu

以上文件如使用請注明出處和作者